1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating floating gates of flash memories.
2. Description of Related Art
Currently, a flash memory with a high memory cell density has significant applications in various apparatus designs. One main advantage of the flash memory is that each memory cell can be fabricated with greatly reduced dimensions, and fabrication cost is also greatly reduced. In a conventional flash memory, memory cells are isolated by a field oxide (FOX) structure that is formed by local oxidation (LOCOS). The dimensions of the FOX structure can only be reduced within certain limits. As a result, cell density is also limited.
Another typical isolation structure is a shallow trench isolation (STI) structure. Since the STI structure can be formed in a much smaller area than the FOX structure, application of the STI structure in a flash memory can effectively minimize the cell dimension so that the cell density can be ultimately increased. FIGS. 1A-1E are schematic, cross-sectional views of a traditional method for fabricating floating gates of flash memories. Reference is made to FIG. 1A, in which a substrate 100 is provided. A tunneling oxide layer 102, a polysilicon layer 104, a silicon nitride layer 106 and patterned photo-resist layer 108 are sequentially formed on the substrate 100. The patterns of the patterned photo-resist layer 108 are photo-resist opening 110 used to define the position of the shallow trenches on the substrate 100.
Reference is made to FIG. 1B, where the photo-resist layer (not shown) is used as a mask, and the silicon nitride layer 106, the polysilicon layer 104, the tunneling oxide layer 102 and the substrate 100 are etched by an anisotropic etching process to form shallow trenches 112. The photo-resist layer is then removed.
In FIG. 1C, the shallow trenches 112 are filled with silicon oxide and shallow trench isolation (STI) structures 114 are formed. The process for forming the STI structures 114 at least comprises a chemical vapor deposition (CVD) process and a planarization process. The silicon oxide is deposited in the shallow trenches and on the surface of the silicon nitride layer 106. A chemical mechanical polishing process is performed to remove the silicon oxide on the silicon nitride layer 106. The silicon nitride layer 106 is a polishing stop layer.
In FIG. 1D, a portion of the STI structures 114 is removed by an anisotropic selective etching process and STI structures 114a are formed. The height of the STI structures 114a is equal to the height of the polysilicon layer 104.
In FIG. 1E, a polysilicon layer 106 is formed, covering the STI structures 114a and the polysilicon layer 104. A lithographic process and an etching process are then performed to remove a portion of the polysilicon layer 116 on the STI structures 114a and to form a floating gate 118. The floating gate 118 consists the polysilicon layers 104 and 116. The purpose of the polysilicon layer 116 is to increase the overlap between the floating gate and the control gate of the flash memory cell. Consequently, the coupling ratio of the flash memory cell will increase. A higher coupling ratio of the flash memory cell can cause a lower electric voltage needed on the gate when the flash memory cell performs an erasure. Additionally, higher coupling ratio of the flash memory cell can also cause a lower necessary electric field for producing Fowler-Nordheim tunneling and thus increase the speed of the electrons transferring between the floating gate and source/drain becomes faster. The speed of reading/writing processes hence increases.
Although traditional manufacturing methods for flash memory cell can provide higher coupling ratios, several disadvantages affect the electricity of the flash memory cell. A process for filling high aspect ratio trenches is the first disadvantage. The window for semiconductor manufacturing process decreases continually as the demand for higher semiconductor device integration increases. Meanwhile, the opening of a trench becomes smaller. With further reference to figure C, the aspect ration of the trenches 112 increases much more than that of trenches fabricated by conventional processes due to the previously formed additional polysilicon layer 104. Seams are formed easily when the high aspect ratio trenches are filled with silicon oxide by a CVD process. Seams are one of the major reasons for the low yield of the flash memory manufacturing processes.
The second disadvantage is related to the bird's beak. Typically, the trench exposes the tunneling oxide layer 112 on its sidewall. A bird's beak occurs when the tunneling oxide layer undergoes a thermal process with oxygen, such as a silicon oxide CVD deposition process. The tunneling oxide layer near the sidewall of the trench then becomes thicker and the electricity of the memory array is altered and does not follow the original design.
With further reference to FIG. 1B, the substrate 100, the tunneling oxide layer 102 and the polysilicon layer 104 form the sidewalls of the trench 112. Performing a STI corner-rounding process on corner 111 of the substrate 100 is very difficult because the tunneling oxide layer 102 and the polysilicon layer 104 are formed thereon. A liner oxide layer (not shown) has to be deposited on the sidewall and bottom of the trench prior to forming the STI structures 114 by a CVD trench filling process. If the corner 111 is not rounded by the STI corner-rounding process, the portion of the liner oxide layer covering this position is thinner. The electricity of the thinner liner oxide layer is reduced and the reliability of the liner oxide layer decreases. The lower reliability of the liner oxide layer is the third disadvantage of the traditional manufacture method for flash memory.
Yet another disadvantage related to the manufacturing process is described with reference to FIG. 1D. Portion of the STI structures are removed by an anisotropic selective etching process and STI structures 114a are formed. The height of the STI structures 114a is equal to the height of the polysilicon layer 104. In practice, it is difficult to form the STI structures 114a to that they are equal to the height of the polysilicon layer 104 in an anisotropic selective etching process. If the height difference between the STI structures 114a and the polysilicon layer 104 exceeds tolerance, the size of the floating gate shown in FIG. 1E will be different; therefore, the electricity of the flash memory cells will different.